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| 51 fax id: 5218 PRELIMINARY CY7C09159 CY7C09169 8K/16K x 9 Synchronous Dual-Port Static RAM Features * True Dual-Ported memory cells which allow simultaneous access of the same memory location * 2 Flow-Through/Pipelined devices -- 8K x 9 organization (CY7C09159) -- 16K x 9 organization (CY7C09169) * 3 Modes -- Flow-Through -- Pipelined -- Burst * Pipelined output mode on both ports allows fast 100-MHz cycle time * 0.35-micron CMOS for optimum speed/power v * High-speed clock to data access 6.5/7.5/12 ns (max.) * Low operating power -- Active= 200 mA (typical) -- Standby= 0.05 mA (typical) * Fully synchronous interface for easier operation * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise * * * * -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Logic Block Diagram R/WL OEL R/WR OER CE0L CE1L 1 0/1 1 0/1 0 0 CE0R CE1R FT/PipeL I/O0L-I/O8L 0/1 1 0 0 1 0/1 FT/PipeR I/O0R-I/O8R 9 9 I/O Control [1] I/O Control 13/14 [1] 13/14 A0-A12/13L CLKL ADSL CNTENL CNTRSTL Counter/ Address Register Decode True Dual-Ported RAM Array Counter/ Address Register Decode A0-A12/13R CLKR ADSR CNTENR CNTRSTR Note: 1. A0-A12 for 8K; A0-A13 for 16K. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 1997 - Revised June 5, 1998 PRELIMINARY Functional Description The CY7C09159 and CY7C09169 are high speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [2] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. CY7C09159 CY7C09169 A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE 0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's address strobe (ADS). When the port's count enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transistion of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Note: 2. When simultaneously writing to the same location, final value cannot be guaranteed. 2 PRELIMINARY CY7C09159 CY7C09169 Pin Configurations 100-Pin TQFP (Top View) CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A0R A1R A2R A3R A4R A5R A6R A6L A5L A4L A3L A2L A1L A0L NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A7L A8L A9L A10L A11L A12L [Note 3] A13L NC NC NC VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 NC NC A7R A8R A9R A10R A11R A12R A13R [Note 3] NC NC NC GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC CY7C09169 (16K x 9) CY7C09159 (8K x 9) NC 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC I/O0R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R GND GND VCC GND VCC I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L Note: 3. This pin is NC for CY7C09159. I/O0L 3 I/01R NC PRELIMINARY Selection Guide CY7C09159 CY7C09169 -6 fMAX2 (MHz) (Pipelined) Max Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) 100 6.5 250 45 0.05 CY7C09159 CY7C09169 -7 83 7.5 235 40 0.05 CY7C09159 CY7C09169 CY7C09159 CY7C09169 -12 50 12 195 30 0.05 Pin Definitions Left Port A0L-A13L ADSL Right Port A0R-A13R ADSR Description Address Inputs. (A0-A12 for 8K; A0-A13 for 16K devices) Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0-I/O7 for x8 devices; I/O0-I/O8 for x9 devices). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current..................................................... >200 mA CE0L,CE1L CLKL CNTENL CE0R,CE1R CLKR CNTENR CNTRSTL I/O0L-I/O 8L OEL R/WL FT/PIPEL GND NC VCC CNTRSTR I/O0R-I/O8R OER R/WR FT/PIPE R Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ..-55C to +125C Supply Voltage to Ground Potential ............... -0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ................................. -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10% 4 PRELIMINARY Electrical Characteristics Over the Operating Range CY7C09159 CY7C09169 -6 Symbol VOH VOL VIH VIL IOZ ICC Parameter Output HIGH Voltage (VCC=Min, IOH=-4.0 mA) Output LOW Voltage (VCC=Min, IOH= +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (V CC=Max, IOUT=0 mA) Outputs Disabled Standby Current (Both Ports TTL Level)[4] CEL & CER VIH, f=fMAX Standby Current (One Port TTL Level)[4] CEL | CER VIH, f=fMAX Standby Current (Both Ports CMOS Level)[4] CEL & CER V CC - 0.2V, f=0 Standby Current (One Port CMOS Level)[4] CEL | CER VIH, f=fMAX Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. Com'l. Indust. 160 200 0.05 0.25 175 235 45 115 -10 250 2.2 0.8 10 450 -10 235 260 40 55 160 175 0.05 0.05 145 160 Min 2.4 0.4 2.2 0.8 10 420 445 105 120 220 235 0.25 0.25 185 200 -10 Typ Max Min 2.4 0.4 2.2 -7 Typ Max Min 2.4 CY7C09159 CY7C09169 -12 Typ Max Units V 0.4 V V 0.8 10 195 225 30 45 125 140 0.05 0.05 110 125 300 375 85 100 190 205 0.25 0.25 150 165 V A mA mA mA mA mA mA mA mA mA mA ISB1 ISB2 ISB3 ISB4 Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads 5V 5V R1 = 893 OUTPUT C = 30 pF R2 = 347 VTH = 1.4V OUTPUT C = 30 pF RTH = 250 R1 = 893 OUTPUT C = 5 pF R2 = 347 (a) Normal Load (Load 1) (b) Thevenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND 10% 3 ns 90% 90% 10% 3 ns (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) Note: 4. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). 5 PRELIMINARY Switching Characteristics Over the Operating Range CY7C09159 CY7C09169 -6 Symbol fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ tCWDD tCCS Parameter fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-up Time Address Hold Time Chip Enable Set-up Time Chip Enable Hold Time R/W Set-up Time R/W Hold Time Input Data Set-up Time Input Data Hold Time ADS Set-up Time ADS Hold Time CNTEN Set-up Time CNTEN Hold Time CNTRST Set-up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Write Port Clock HIGH to Read Data Delay Clock to Clock Set-up Time Min Max 53 100 19 10 6.5 6.5 4 4 3 3 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 8 2 1 7 15 6.5 9 2 1 4 0 4 0 4 0 4 0 4 0 4 0 4 0 9 7 18 7.5 9 2 1 22 12 7.5 7.5 5 5 3 3 4 1 4 1 4 1 4 1 4 1 4 1 4 1 Min -7 Max 45 83 30 20 12 12 8 8 Min CY7C09159 CY7C09169 -12 Max 33 50 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 12 7 25 12 9 2 2 2 2 2 2 2 2 2 Port to Port Delays 30 9 35 10 40 15 6 PRELIMINARY Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V IL)[5,6,7,8] tCH1 CLK tCYC1 tCL1 CY7C09159 CY7C09169 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT tCKLZ tOHZ OE tOE tOLZ An tCD1 tHW tHA An+1 tDC Qn Qn+1 An+2 An+3 tCKHZ Qn+2 tDC Read Cycle for Pipelined Operation (FT/PIPE = VIH)[5,6,7,8] tCH2 CLK tCYC2 tCL2 CE0 tSC CE1 tHC tSC tHC R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE tOE Notes: 5. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 6. ADS = VIL, CNTEN and CNTRST = VIH. 7. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 8. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. An+2 tDC Qn+1 tOHZ An+3 Qn+2 tOLZ 7 PRELIMINARY Switching Waveforms (continued) Bank Select Pipelined Read[9,10] tCYC2 CY7C09159 CY7C09169 tCH2 CLK L tSA ADDRESS(B1) tSC CE 0(B1) A0 tCL2 tHA A1 tHC A2 A3 A4 A5 tCD2 DATAOUT(B1) tSA ADDRESS (B2) A0 tHA A1 tSC CE 0(B2) tSC DATAOUT(B2) tHC tSC D0 tHC tCD2 D1 tCKHZ tCD2 D3 tCKHZ tDC A2 tHC tDC A3 A4 tCKLZ A5 tCD2 D2 tCKLZ tCKHZ tCD2 D4 tCKLZ Left Port Write to Flow-Through Right Port Read[11,12,13,14] CLK L tSW R/WL tSA ADDRESS L tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH tHW MATCH Notes: 9. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2. Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 10. OE and ADS = VIL ; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 11. The same waveforms apply for a right port write to flow-through left port read. 12. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 13. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 14. It t CCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. t CWDD does not apply in this case. 8 PRELIMINARY Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = VIL)[8,12,15,16] tCH2 CLK tCYC2 tCL2 CY7C09159 CY7C09169 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION WRITE READ tCKHZ tHW An+1 An+2 An+2 tSD tHD Dn+2 tCKLZ tCD2 Qn+3 An+3 An+4 tHW tHC DATAOUT Pipelined Read-to-Write-to-Read (OE Controlled)[8,12,15,16] tCH2 CLK tCYC2 tCL2 CE 0 tSC tHC CE 1 tSW tHW R/W tSW An tHW An+1 tHA An+2 tSD tHD Dn+2 tCD2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5 ADDRESS tSA DATAOUT DATAIN OE READ WRITE READ Notes: 15. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 16. During "No operation", data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. 9 PRELIMINARY Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = VIL)[6,8,12,15] tCH1 CLK tCYC1 tCL1 CY7C09159 CY7C09169 CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC DATAOUT Flow-Through Read-to-Write-to-Read (OE Controlled)[6,8,12,15] tCYC1 tCL1 tCH1 CLK CE0 tSC CE1 tSW R/W tSW An ADDRESS tSA DATAIN tCD1 Qn tOHZ tCKLZ tHA tDC tSD Dn+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 tHW An+1 An+2 An+3 An+4 An+5 tHW tHC DATAOUT OE READ WRITE READ 10 PRELIMINARY Switching Waveforms (continued) Pipelined Read with Address Counter Advance[17] tCYC2 tCL2 CY7C09159 CY7C09169 tCH2 CLK tSA ADDRESS tSAD ADS An tHA tHAD tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC READ WITH COUNTER tCD2 Qn tSCN Qn+1 tHAD tHCN Qn+2 Qn+3 COUNTER HOLD READ WITH COUNTER Flow-Through Read with Address Counter Advance[17] tCYC1 tCL1 tCH1 CLK tSA ADDRESS tSAD ADS An tHA tHAD tSAD tHAD CNTEN tSCN tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 Qn+2 tSCN tHCN DATA OUT Qn+3 READ WITH COUNTER READ WITH COUNTER COUNTER HOLD Note: 17. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. 11 PRELIMINARY Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[18,19] tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 CY7C09159 CY7C09169 INTERNAL ADDRESS tSAD ADS tHAD An An+1 An+2 An+3 An+4 CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4 WRITE COUNTER HOLD WRITE WITH COUNTER Notes: 18. CE0 and R/W = VIL ; CE1 and CNTRST = VIH. 19. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 12 PRELIMINARY Switching Waveforms (continued) Counter Reset (Pipelined Outputs)[8,15,20,21] tCYC2 tCL2 CY7C09159 CY7C09169 tCH2 CLK tSA ADDRESS INTERNAL ADDRESS AX tSW tHW 0 1 An tHA An+1 An An+1 R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN tHRST tSD D0 Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 READ ADDRESS n Qn tHD tHCN tHAD DATAOUT Notes: 20. CE0 = VIL; CE1 = VIH. 21. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 13 PRELIMINARY Read/Write and Enable Operation[22,23,24] Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O 0-I/O8 High-Z High-Z DIN DOUT High-Z Operation Deselected[25] Deselected[25] Write Read[25] Outputs Disabled CY7C09159 CY7C09169 Address Counter Control Operation[22,26,27,28] Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked--Counter Disabled Counter Enabled--Internal Address Generation Notes: 22. "X" = Don't Care, "H" = VIH, "L" = VIL. 23. ADS, CNTEN, CNTRST = Don't Care. 24. OE is an asynchronous input signal. 25. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 26. CE0 and OE = VIL; CE1 and R/W = VIH. 27. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle. 28. Counter operation is independent of CE0 and CE1. 14 PRELIMINARY Ordering Information 8K x9 Synchronous Dual-Port SRAM Speed (ns) 6.5 7.5 12 Ordering Code CY7C09159-6AC CY7C09159-7AC CY7C09159-7AI CY7C09159-12AC CY7C09159-12AI 16K x9 Synchronous Dual-Port SRAM Speed (ns) 6.5 7.5 12 Ordering Code CY7C09169-6AC CY7C09169-7AC CY7C09169-7AI CY7C09169-12AC CY7C09169-12AI Document #: 38-00671-B Package Name A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Package Name A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack CY7C09159 CY7C09169 Operating Range Commercial Commercial Industrial Commercial Industrial Operating Range Commercial Commercial Industrial Commercial Industrial Package Diagram 100-Pin Thin Quad Flat Pack A100 (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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